oa2a22 standard cell family

2×2-AND into 2-OR gate
oa2a22 symbol
2-2 I/P AND-OR gate with a stage effort of about 3.5 for the oa2a22_x2, and about 7 for the oa2a22_x4.
q:((i2*i3)+(i0*i1)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oa2a22_x2 3.0  90 4.95 1.39  28.6  3.7f 104  1.52 133  1.23
oa2a22_x4 3.3 100 5.50 2.08  45.3  3.6f 134  0.77 174  0.63
oa2a22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.04
i1 /\
¯_ 1.99
i2 /\
¯_ 2.39
i3 /\
¯_ 2.44
oa2a22_x2 schematic oa2a22_x2 standard cell layout
oa2a22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.41
i1 /\
¯_ 2.35
i2 /\
¯_ 2.76
i3 /\
¯_ 2.82
oa2a22_x4 schematic oa2a22_x4 standard cell layout