a2 standard cell family

2-I/P AND gate
a2 symbol
2 I/P AND gate with a stage effort of about 1.8 for the a2_x2 and about 3.6 for the a2_x4.
q:(i1*i0) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a2_x2 1.7  50 2.75 1.16  28.7  4.9f  69  1.52  96  1.20
a2_x4 2.0  60 3.30 2.08  44.3  4.5f  89  0.76 119  0.61
a2_x2
 
Effort
FO4 Log.
i0 /\
¯_ 1.57
i1 /\
¯_ 1.70
a2_x2 schematic a2_x2 standard cell layout
a2_x4
 
Effort
FO4 Log.
i0 /\
¯_ 1.67
i1 /\
¯_ 1.77
a2_x4 schematic a2_x4 standard cell layout