a3 standard cell family

3-I/P AND gate
a3 symbol
3 I/P AND gate designed with a stage effort of about 2.1 for the a3_x2 and about 4.2 for the a3_x4.
q:(i0*i1*i2) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a3_x2 2.0  60 3.30 1.62  38.3  4.9f  99  1.52 124  1.21
a3_x4 2.3  70 3.85 2.31  54.0  4.7f 124  0.77 147  0.61
a3_x2
 
Effort
FO4 Log.
i0 /\
¯_ 1.78
i1 /\
¯_ 1.90
i2 /\
¯_ 1.98
a3_x2 schematic a3_x2 standard cell layout
a3_x4
 
Effort
FO4 Log.
i0 /\
¯_ 1.95
i1 /\
¯_ 2.05
i2 /\
¯_ 2.13
a3_x4 schematic a3_x4 standard cell layout