xnr2 standard cell family

2-I/P exclusive NOR gate
xnr2 symbol
2-input XNOR gate with output P/N ratio of about 1.25. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnr2v0x1 4.0  96 5.28 1.66  32.7  5.7f  90  3.36  76  1.53
xnr2v0x1
 
Effort
FO4 Log.
a /\ 1.63 1.32
¯_ 2.35
b /\ 1.85 2.44
¯_ 2.67
xnr2v0x1 schematic xnr2v0x1 standard cell layout