nd4 standard cell family

 4-I/P NAND gate
nd4 symbol
The P/N ratio is set to 2.5, which is close to the P/N ratio of 2.6 which gives the fastest speed, as well as balanced rise and fall drive strengths.
z:(a*b*c*d)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd4_x05 2.0  60 3.30  0.84   9.2  3.5f  56  4.25  42  3.83
nd4_x1 2.0  60 3.30 1.62  16.4  6.2f  54  2.20  41  2.02
nd4_x2 3.0  90 4.95 2.33  22.7  8.7f  52  1.52  40  1.41
nd4_x3 3.7 110 6.05 3.12  30.5 11.7f  53  1.13  40  1.05
nd4_x05
 
Effort
FO4 Log.
a /\ 1.84 1.71
¯_
b /\ 1.77 1.72
¯_
c /\ 1.67 1.71
¯_
d /\ 1.51 1.64
¯_
nd4_x05 schematic nd4_x05 standard cell layout
nd4_x1
 
Effort
FO4 Log.
a /\ 1.74 1.59
¯_
b /\ 1.68 1.60
¯_
c /\ 1.57 1.58
¯_
d /\ 1.43 1.52
¯_
nd4_x1 schematic nd4_x1 standard cell layout
nd4_x2
 
Effort
FO4 Log.
a /\ 1.77 1.65
¯_
b /\ 1.69 1.64
¯_
c /\ 1.56 1.59
¯_
d /\ 1.40 1.49
¯_
nd4_x2 schematic nd4_x2 standard cell layout
nd4_x3
 
Effort
FO4 Log.
a /\ 1.77 1.66
¯_
b /\ 1.70 1.66
¯_
c /\ 1.55 1.56
¯_
d /\ 1.40 1.49
¯_
nd4_x3 schematic nd4_x3 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008