nd2ab standard cell family

 2-I/P OR gate
nd2ab symbol
The nd2ab gates are 2-OR gates made up as 2 inverters driving a NAND gate. According to the theory of logical effort, this combination should be faster than a regular or2 gate, and it is. The speed can be compared to the or2 gates, especially the or2v0x1 which has the same output P-transistor size as the nd2abv0x1. The nd2ab gates are bigger and consume more power than the or2 gates.
z:(a+b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2ab_x1 2.0  60 3.30 1.28  19.4  3.4f  69  2.97  76  2.16
nd2ab_x2 2.3  70 3.85 2.25  34.3  5.2f  72  1.52  80  1.11
nd2ab_x1
 
Effort
FO4 Log.
a /\
¯_ 1.63
b /\
¯_ 1.54
nd2ab_x1 schematic nd2ab_x1 standard cell layout
nd2ab_x2
 
Effort
FO4 Log.
a /\
¯_ 1.55
b /\
¯_ 1.48
nd2ab_x2 schematic nd2ab_x2 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008