nd2 standard cell family

 2-I/P NAND gate
nd2 symbol
Single stage 2-I/P NAND gates. 4 drive strengths with a P/N ratio of 2.
z:(a*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2_x05 1.3  40 2.20  0.39   4.8  2.5f  45  4.94  35  3.68
nd2_x1 1.3  40 2.20  0.66   7.8  4.0f  44  2.96  35  2.16
nd2_x2 1.3  40 2.20 1.28  14.3  7.5f  43  1.52  34  1.11
nd2_x4 2.0  60 3.30 2.50  26.1 14.2f  42  0.78  33  0.56
nd2_x05
 
Effort
FO4 Log.
a /\ 1.25 1.29
¯_
b /\ 1.20 1.27
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nd2_x05 schematic nd2_x05 standard cell layout
nd2_x1
 
Effort
FO4 Log.
a /\ 1.21 1.22
¯_
b /\ 1.16 1.19
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nd2_x1 schematic nd2_x1 standard cell layout
nd2_x2
 
Effort
FO4 Log.
a /\ 1.17 1.18
¯_
b /\ 1.12 1.15
¯_
nd2_x2 schematic nd2_x2 standard cell layout
nd2_x4
 
Effort
FO4 Log.
a /\ 1.16 1.18
¯_
b /\ 1.09 1.12
¯_
nd2_x4 schematic nd2_x4 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008