cgi2 standard cell family

 carry generator inverting
cgi2 symbol
The output is the inverted carry of bits a and b and carry input c, with the delay from pin c being favoured. The cells here use a P/N ratio of 2.
z:((a*b)+(a*c)+(b*c))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgi2_x05 2.3  70 3.85  0.67   9.7  3.1f  57  5.85  52  4.09
cgi2_x1 2.3  70 3.85 1.32  18.0  5.8f  55  3.00  50  2.04
cgi2_x2 4.3 130 7.15 2.48  34.3 10.5f  56  1.58  51  1.10
cgi2_x05
 
Effort
FO4 Log.
a /\ 2.70 3.49
¯_
b /\ 2.67 3.50
¯_
c /\ 1.68 1.82
¯_
cgi2_x05 schematic cgi2_x05 standard cell layout
cgi2_x1
 
Effort
FO4 Log.
a /\ 2.60 3.38
¯_
b /\ 2.56 3.34
¯_
c /\ 1.60 1.71
¯_
cgi2_x1 schematic cgi2_x1 standard cell layout
cgi2_x2
 
Effort
FO4 Log.
a /\ 2.67 3.53
¯_
b /\ 2.50 3.25
¯_
c /\ 1.57 1.64
¯_
cgi2_x2 schematic cgi2_x2 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008