aon21 standard cell family

 2-AND into 2-OR gate
aon21 symbol
2 cells with different drive strengths, each with a P:N ratio of about 2. The aon21_x1 has a stage effort of about 1.7 and the aon21_x2 about 2.2.
z:((a1*a2)+b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aon21_x1 2.3  70 3.85  0.92  23.6  4.5f  92  2.98 110  2.29
aon21_x2 2.3  70 3.85 1.41  37.7  6.3f  97  1.57 114  1.21
aon21_x1
 
Effort
FO4 Log.
a1 /\
¯_ 2.20
a2 /\
¯_ 2.13
b /\
¯_ 1.81
aon21_x1 schematic aon21_x1 standard cell layout
aon21_x2
 
Effort
FO4 Log.
a1 /\
¯_ 2.07
a2 /\
¯_ 2.01
b /\
¯_ 1.70
aon21_x2 schematic aon21_x2 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008