na4 standard cell family

 4-I/P NAND gate
na4 symbol
The na4_x1 is a single stage 4-NAND with P/N ratio of about 3. The na4_x4 is a 3 stage 4-NAND with stage efforts of about 1.2 and 3.9.
nq:(i0*i1*i2*i3)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i3.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
na4_x1 2.0  60 3.30 1.16  12.8  4.4f  55  2.97  51  3.62
na4_x4 3.3 100 5.50 2.89  60.4  4.8f 154  0.76 180  0.61
na4_x1
 
Effort
FO4 Log.
i0 /\ 1.80 1.66
¯_
i1 /\ 1.79 1.75
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i2 /\ 1.69 1.71
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i3 /\ 1.59 1.68
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na4_x1 schematic na4_x1 standard cell layout
na4_x4
 
Effort
FO4 Log.
i0 /\ 2.85 0.36
¯_
i1 /\ 2.79 0.38
¯_
i2 /\ 2.69 0.38
¯_
i3 /\ 2.58 0.38
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na4_x4 schematic na4_x4 standard cell layout
Web data book for the ssxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008