halfadder standard cell family

 2-I/P half adder
halfadder symbol
2 I/P half adder with carry and sum outputs.
cout:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  79.2 10.8f  98  1.52 105  1.21
halfadder_x4 6.0 180 9.90 4.64 121.4 10.7f 126  0.77 133  0.61
sout:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
halfadder_x2 5.3 160 8.80 3.26  68.7 10.8f 136  1.52 162  1.23
halfadder_x4 6.0 180 9.90 4.64 101.1 10.7f 165  0.77 203  0.63
halfadder_x2
 
Effort
FO4 Log.
a /\ 3.38 1.68
¯_ 2.62
b /\ 2.99 1.64
¯_ 2.78
halfadder_x2 schematic halfadder_x2 standard cell layout
halfadder_x4
 
Effort
FO4 Log.
a /\ 3.48 0.85
¯_ 2.67
b /\ 3.09 0.82
¯_ 2.92
halfadder_x4 schematic halfadder_x4 standard cell layout
Web data book for the ssxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008