a4 standard cell family

 4-I/P AND gate
a4 symbol
4 I/P AND gate designed with a stage effort of about 2.4 for the a4_x2 and about 4.8 for the a4_x4.
q:(i0*i1*i2*i3) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i3.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a4_x2 2.3  70 3.85 1.85  32.6  4.7f 112  1.57 110  1.21
a4_x4 2.7  80 4.40 2.54  48.3  4.5f 138  0.79 134  0.61
a4_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.22
i1 /\
¯_ 2.17
i2 /\
¯_ 2.07
i3 /\
¯_ 1.97
a4_x2 schematic a4_x2 standard cell layout
a4_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.38
i1 /\
¯_ 2.32
i2 /\
¯_ 2.25
i3 /\
¯_ 2.13
a4_x4 schematic a4_x4 standard cell layout
Web data book for the ssxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008