## Review of Terms Used in Describing Logical Effort

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This review of logical effort examines the values of logical effort used in the book Logical Effort, Designing Fast CMOS Circuits by Ivan Sutherland, Bob Sproull and David Harris. Slightly different values of logical effort are proposed and have been used in the design of the cells in the vsclib.

The terminology is consistent with that in Logical Effort, and is listed here. The value of γ could be any reasonable value. The ones listed are the ones used in the vsclib cells.

 4-NOR 3-NOR 2-NOR INV 2-NAND 3-NAND 4-NAND NN Number of series N transistors 1 1 1 1 2 3 4 NP Number of series P transistors 4 3 2 1 1 1 1 KN N transistor conductivity coefficient 1 1 1 1 5/3 7/3 3 KP P transistor conductivity coefficient 29/8 22/8 15/8 1 1 1 1 k series transistor compensating factor k=KP/KN 29/8 22/8 15/8 1 3/5 3/7 1/3 γ P:N transistor ratio (called shape factor in Logical Effort) 2 2 2 2 2 2.33 2.5 r drawn P:N width ratio r=KP·γ/KN 7.25 5.5 3.75 2 1.2 1 0.83 µn mobility of N transistor µp mobility of P transistor µ N:P transistor mobility ratio µ=µn/µp µ=2.25 used in vsclib g logical effort see below 2.70 2.13 1.55 0.98 1.20 1.41 1.61

In Logical Effort, the values for KP and KN are set equal to the values for NP and NN. Generally, a value of µ=2 is used rather than the vsclib value of µ=2.25.

The following pages explain why these values have been chosen and derive the general expression for logical effort g used in the vsclib:
g = ½×(KP·γ+KN+KP·µ+KN·µ/γ)/(1+µ).

Designing cells in a good way so as to minimise logical effort is important because the delay directly depends on it. Good cell design means a correct choice of transistor sizes and attention to minimising parasitic capacitances. These characteristics are not always found in standard cell libraries.