## Logical Effort of Complex Inverting Gates

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 Logical effort of different complex gates, from Logical Effort book NAND gates' series N transistors 1 2 3 4 NOR gates' series P transistors 1 1.00 1.33 1.67 2.00 2 1.67 2.00 2.33 2.67 3 2.33 2.67 3.00 3.33 4 3.00 3.33 3.67 4.00

From the analysis on NAND and NOR gates, we can extend the equation for logical effort to the case of an arbitrary number of series N and P transistors. A table of logical effort for all combinations of inverting complex gates from 1-4 series transistors can be drawn up using Ohm's law and µ=2, as in Logical Effort.

 Logical effort of different complex gates used in the vsclib NAND gates' series N transistors 1 2 3 4 NOR gates' series P transistors 1 0.98 1.20 1.41 1.61 2 1.55 1.77 1.99 2.21 3 2.13 2.34 2.56 2.78 4 2.70 2.92 3.13 3.35

This can be compared with a table of logical effort used for the vsclib design. The derivation of the numbers in this table is shown below.

### Selecting the P:N Transistor Ratio for Complex Gates

In order to calculate the falling logical effort, the N transistors are sized so that the conductivity of the series transistors is the same as a single N transistor with a width of 1. For a complex gate with P:N transistor ratio of γ this means that the equivalent inverter has a drive of (P=γ,N=1), and the complex gate has (P=KP·γ,N=KN). Then the falling logical effort is
gd = (KN+KP·γ)/(1+µ)
For the rising logical effort, we scale the P transistor of the equivalent inverter to P=µ. The N transistor is then scaled by a factor of µ/γ from this. The series P transistor of the complex gate is then KP× bigger than the equivalent inverter, and the series N transistor is KN× bigger. This gives a rising logical effort of
gu = (KP·µ+KN·µ/γ)/(1+µ)
The logical effort g is then:
g = ½×(KP·γ+KN+KP·µ+KN·µ/γ)/(1+µ)

This is quite a useful result, as it is generic and applies as well to inverters, NAND and NOR gates.

The fastest gates can be found when
dg/dγ = 0 = KP-KN·µ2
from which γ = √(KN·µ/KP) for the fastest gates.

 Value of γ for the fastest versions of different complex gates NAND gates' series N transistors 1 2 3 4 NOR gates' series P transistors 1 1.50 1.94 2.29 2.60 2 1.10 1.41 1.67 1.90 3 0.90 1.17 1.38 1.57 4 0.79 1.02 1.20 1.36

We use this expression to draw up a table of the γ values for the fastest gates for all gates with up to 4 series P or N transistors. Our design policy is to have a lower value of γ=2 and an upper value of γ=2.5 in order to keep the output rise and fall drive strengths reasonably balanced. From this table, we can see that all gate types will have γ=2 except for the 3-NAND and 4-NAND, which as we have already seen, will use values of γ=2.33 and γ=2.5.

 Value of γ chosen for the different vsclib complex gates NAND gates' series N transistors 1 2 3 4 NOR gates' series P transistors 1 2 2 2.33 2.5 2 2 2 2 2 3 2 2 2 2 4 2 2 2 2

Now for each gate type, we have values of P:N transistor ratio (γ), P and N transistor conductivity coefficients (KP,KN), and a value for mobility µ=2.25. Thus for each gate type we can calculate the logical effort
g = ½×(KP·γ+KN+KP·µ+KN·µ/γ)/(1+µ).
This gives us the table at the top of the page, showing logical effort for all 16 inverting gate types with 1-4 series transistors.

 Logical effort of different complex gates used in the vsclib NAND gates' series N transistors 1 2 3 4 NN 3/3 5/3 7/3 9/3 KN NOR gates' series P transistors 1 8/8 0.98 1.20 1.41 1.61 2 15/8 1.55 1.77 1.99 2.21 3 22/8 2.13 2.34 2.56 2.78 4 29/8 2.70 2.92 3.13 3.35 NP KP g = ½×(KP·γ+KN+KP·µ+KN·µ/γ)/(1+µ)