Conclusions and Further Work
This experiment has developed an improved Alliance synthesis
flow and used it to help in deciding which cells to include
in a standard cell library. The improved flow:
- Uses wireloads for synthesis to help ensure that the netlist
is suitably buffered.
- Uses netlists and associated timing files to allow the
synthesis to select higher drive cells than are available as
library primitives. This means that a function on the critical
path which only has a weak drive strength can be buffered up
- Uses separate libraries for BOOG and LOON
synthesis. This allows a better control over the netlist
produced by BOOG and ensures that it starts with the
weakest drive strength cells so that LOON can buffer them up
- Uses separate libraries, one with buffers defined and one
without, so that the initial LOON synthesis runs will not
insert buffers onto false critical paths.
- Switches the LOON synthesis between two wireload values
(0fF and 6fF have been used) so that each synthesis finds some
improvement and can help move the critical path around local minima.
A complete synthesis job is a succession of LOON runs
giving an incremental improvement until the synthesis iterates to
a final timing and area value.
- Uses scripts to do jobs which LOON cannot handle
unaided. These include inserting buffers on the inputs to keep
down the input capacitance and speed up the critical path;
buffering the outputs to a desired drive strength; and manually
resizing internal cells when LOON fails to find the best
- Uses diagnostic scripts which help understand the netlist better.
These list critical paths, input capacitances, fanin etc.
The improved flow is targeted at improving the speed of the
netlist critical path. This is basically done by setting the
cells on the critical path to a high drive strength while keeping
the other cells weak. The higher drive strength cells are bigger,
so this timing improvement will be at the cost of increased area.
The results are compared to the best regular Alliance synthesis
from experiment 22.
delay in ps
delay in ps
|standard Alliance flow, BOOG then LOON
With this new flow, and starting from a very basic library,
cells are added in stages and the timing improvement monitored.
At the end of this phase, the library has 188 cells. Cells are then
removed until a maximum acceptable loss of performance has
been reached. This library has 92 cells.
Further work which will be presented later includes:
- Adding non-inverting functions (like the aon21,
the inverse of the aoi21). Only the basic AND and OR
gates have been included so far.
- Adding cells with a skewed P:N transistor ratio.
- Adding functions with inverted inputs, in addition to the
nd2a and nr2a.
- Adding more XOR type functions with incorporated AND and/or
- Adding more cells with transfer gate type logic.