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Further information

The Alliance software needs timing files in a VBE format for its synthesis and simulation; and layout in its own AP format for its place and route, design rule checks and LVS.

The library cells have been drawn with Graal. This creates AP layout files in a technology independent format. With the appropriate RDS file, CIF, GDS and Spice decks can be output in different technologies. RDS files to convert the layout to a generic 0.13um technology can be found here.

The Alliance conversion algorithms from AP to CIF, GDS and Spice are not very powerful. In fact, the 0.13µm CIF files written from Graal will not pass a DRC check. Instead the CIF file is read into Magic and from here are written the good quality CIF, GDS and Spice decks.

The Alliance sxlib is supplied with 0.35µm timing numbers. The other libraries have estimated timing numbers (the spice deck which was used for the sxlib timing isn't available, so proper characterisation can't be done) and the characterisation script replaces these estimated 0.35µm numbers with the real 0.13µm values.

An example VBE file.

ENTITY iv1v0x2 IS
  CONSTANT area          : NATURAL := 1728;   
  CONSTANT cin_a         : NATURAL := 5;      
  CONSTANT rdown_a_z     : NATURAL := 1650;   
  CONSTANT rup_a_z       : NATURAL := 2120;   
  CONSTANT tphl_a_z      : NATURAL := 33;     
  CONSTANT tplh_a_z      : NATURAL := 38;     
  CONSTANT transistors   : NATURAL := 2       
  a	 : in  BIT;
  z	 : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
END iv1v0x2;

ARCHITECTURE behaviour_data_flow OF iv1v0x2 IS

  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on iv1v0x2"
  z <= not (a) after 700 ps;

An example AP file.

H iv1v0x2,P, 1/ 6/2006,1000
A 0,0,24000,72000
R 4000,48000,ref_ref,z_48
R 4000,40000,ref_ref,z_40
R 4000,32000,ref_ref,z_32
R 4000,24000,ref_ref,z_24
R 4000,16000,ref_ref,z_16
R 20000,48000,ref_ref,a_48
R 20000,40000,ref_ref,a_40
R 20000,32000,ref_ref,a_32
R 12000,48000,ref_ref,z_48
R 12000,32000,ref_ref,a_32
S 5000,41000,5000,49000,4000,*,UP,POLY2
S 5000,40000,5000,50000,6000,*,UP,PDIF
S 5000,15000,5000,24000,4000,*,UP,POLY2
S 5000,14000,5000,23000,6000,*,UP,NDIF
S -4000,56000,-4000,56000,4000,*,LEFT,TALU1
S 4000,48000,12000,48000,6000,*,RIGHT,ALU1
S 4000,40000,20000,40000,20000,*,RIGHT,TALU1
S 4000,24000,28000,24000,4000,*,RIGHT,TALU1
S 4000,16000,4000,48000,4000,z,UP,CALU1
S 4000,16000,20000,16000,4000,*,RIGHT,TALU1
S 4000,15000,4000,49000,4000,*,UP,ALU1
S 20000,32000,20000,48000,4000,a,UP,CALU1
S 20000,31000,20000,49000,4000,*,UP,ALU1
S 16000,40000,16000,64000,6000,*,UP,PDIF
S 16000,14000,16000,24000,6000,*,UP,NDIF
S 15000,56000,15000,68000,6000,*,UP,POLY2
S 15000,4000,15000,23000,4000,*,UP,POLY2
S 12000,56000,28000,56000,4000,*,RIGHT,TALU1
S 12000,48000,12000,48000,4000,z,LEFT,CALU1
S 12000,32000,20000,32000,6000,*,RIGHT,ALU1
S 12000,32000,12000,32000,4000,a,LEFT,CALU1
S 10000,8000,10000,12000,2000,*,UP,POLY
S 10000,38000,10000,66000,2000,01,UP,PTRANS
S 10000,32000,12000,32000,6000,*,RIGHT,POLY
S 10000,12000,10000,26000,2000,02,UP,NTRANS
S 0,68000,24000,68000,8000,vdd,RIGHT,CALU1
S 0,68000,24000,68000,8000,*,RIGHT,ALU1
S 0,54000,24000,54000,44000,*,RIGHT,NWELL
S 0,4000,24000,4000,8000,vss,RIGHT,CALU1
S 0,4000,24000,4000,8000,*,RIGHT,ALU1
S 0,36000,24000,36000,72000,iv1v0x2,RIGHT,TALU8
S 0,14000,24000,14000,36000,*,RIGHT,PWELL
V 5000,49000,CONT_DIF_P,*
V 5000,42000,CONT_DIF_P,*
V 5000,23000,CONT_DIF_N,*
V 5000,16000,CONT_DIF_N,*
V 15000,63000,CONT_DIF_P,*
V 15000,56000,CONT_DIF_P,*
V 15000,22000,CONT_DIF_N,*
V 15000,15000,CONT_DIF_N,*
V 13000,32000,CONT_POLY,*