nr3ab standard cell family

 3-I/P NOR gate with two inverted inputs
nr3ab symbol
Minimum size 3-I/P NOR gate with 2 inverted inputs, made from a 2-I/P NAND followed by a 2-I/P NOR. The output P/N ratio is about 2, and the gain from inputs a and b is about 1.6.
z:(a'+b'+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr3abv0x05 2.0  48 2.64  0.76   5.2  3.0f  46  5.81  41  3.86
nr3abv0x05
 
Effort
FO4 Log.
a /\
¯_ 2.24
b /\
¯_ 2.15
c /\ 1.47 1.72
¯_
nr3abv0x05 schematic nr3abv0x05 standard cell layout
Web data book for the wsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008