iv1 standard cell family

inverter
iv1 symbol
   v0  P/N=2
   v1 P/N=1.5
   v2 P/N=2.25
   v3 P/N=1
   v4 P/N=4
   v5 P/N=2.6

Inverters with different drive strengths and P/N ratios.
The P/N ratios used for each version are shown to the right. The P:N ratio of 2 offers good output skew and speed, while 1.5 is close to the fastest speed. 2.25 is a balanced ratio if the mobility ratio µ equals 2.25 and 2.6 is balanced for this techno where µ is close to 2.6. P/N ratios of 1 and 4 give heavily skewed outputs for specific applications.
The v6, v7 and v8 versions are experimental cells. The iv1v2x2 is considered as the reference inverter for logical effort calculations.

z:a' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
iv1v0x05 1.0  24 1.32  0.21   3.3  2.1f  39  4.93  33  3.84
iv1v1x05 1.0  24 1.32  0.23   3.5  2.3f  40  4.93  30  2.92
iv1v0x1 1.0  24 1.32  0.31   4.8  3.0f  39  3.29  33  2.56
iv1v1x1 1.0  24 1.32  0.35   5.2  3.4f  40  3.29  30  1.95
iv1v3x1 1.0  24 1.32  0.46   6.4  4.2f  42  3.11  25  1.27
iv1v4x1 1.0  24 1.32  0.35   5.2  3.3f  35  2.49  41  3.81
iv1v5x1 1.0  24 1.32  0.29   4.4  2.9f  37  3.29  36  3.27
iv1v6x1 1.0  24 1.32  0.31   5.0  3.2f  39  3.29  34  2.56
iv1v7x1 1.0  24 1.32  0.31   4.7  3.1f  38  3.29  33  2.56
iv1v8x1 1.0  24 1.32  0.27   4.0  2.4f  39  3.94  35  3.27
iv1v0x2 1.0  24 1.32  0.48   7.1  4.6f  38  2.11  33  1.65
iv1v1x2 1.0  24 1.32  0.54   7.8  5.2f  39  2.11  29  1.23
iv1v2x2 1.0  24 1.32  0.45   6.4  4.2f  37  2.19  34  1.91
iv1v4x2 1.3  32 1.76  0.46   5.8  4.3f  34  1.86  39  2.85
iv1v5x2 1.0  24 1.32  0.45   6.6  4.4f  37  2.12  36  2.08
iv1v6x2 1.0  24 1.32  0.45   7.2  4.7f  38  2.12  33  1.65
iv1v0x3 1.3  32 1.76  0.69   8.4  6.5f  36  1.48  31  1.14
iv1v3x3 1.3  32 1.76  0.92  10.9  8.9f  40  1.48  23  0.61
iv1v4x3 1.3  32 1.76  0.69   8.3  6.2f  34  1.27  38  1.90
iv1v5x3 1.3  32 1.76  0.64   8.0  5.8f  35  1.48  34  1.53
iv1v0x4 1.3  32 1.76  0.97  11.4  9.0f  36  1.06  31  0.83
iv1v1x4 1.3  32 1.76 1.09  12.6 10.2f  37  1.06  27  0.62
iv1v4x4 1.7  40 2.20  0.98  12.2  9.0f  34  0.88  39  1.34
iv1v5x4 1.3  32 1.76  0.90  10.5  8.3f  35  1.06  33  1.04
iv1v0x6 1.7  40 2.20 1.40  16.7 12.9f  36  0.73  31  0.57
iv1v3x6 2.3  56 3.08 1.85  21.3 17.7f  39  0.74  23  0.31
iv1v4x6 2.3  56 3.08 1.39  15.7 12.6f  33  0.62  38  0.95
iv1v5x6 1.7  40 2.20 1.34  16.1 12.3f  35  0.71  34  0.72
iv1v0x8 2.3  56 3.08 1.80  21.0 16.8f  36  0.56  31  0.44
iv1v1x8 2.3  56 3.08 2.00  23.3 18.8f  37  0.56  28  0.34
iv1v4x8 2.7  64 3.52 1.85  21.2 16.8f  33  0.47  38  0.71
iv1v5x8 2.3  56 3.08 1.66  19.0 15.2f  35  0.56  33  0.56
iv1v0x12 3.0  72 3.96 2.77  31.7 25.6f  36  0.37  31  0.28
iv1v4x12 3.0  72 3.96 2.31  25.6 21.0f  32  0.38  37  0.56
iv1v5x12 3.0  72 3.96 2.56  29.4 23.4f  35  0.37  33  0.37
iv1v0x05
 
Effort
FO4 Log.
a /\ 1.04 1.06
¯_
iv1v0x05 schematic iv1v0x05 standard cell layout
iv1v1x05
 
Effort
FO4 Log.
a /\ 1.02 1.06
¯_
iv1v1x05 schematic iv1v1x05 standard cell layout
iv1v0x1
 
Effort
FO4 Log.
a /\ 1.02 1.03
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iv1v0x1 schematic iv1v0x1 standard cell layout
iv1v1x1
 
Effort
FO4 Log.
a /\ 1.01 1.04
¯_
iv1v1x1 schematic iv1v1x1 standard cell layout
iv1v3x1
 
Effort
FO4 Log.
a /\ 1.02 1.08
¯_
iv1v3x1 schematic iv1v3x1 standard cell layout
iv1v4x1
 
Effort
FO4 Log.
a /\ 1.14 1.21
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iv1v4x1 schematic iv1v4x1 standard cell layout
iv1v5x1
 
Effort
FO4 Log.
a /\ 1.07 1.11
¯_
iv1v5x1 schematic iv1v5x1 standard cell layout
iv1v6x1
 
Effort
FO4 Log.
a /\ 1.06 1.08
¯_
iv1v6x1 schematic iv1v6x1 standard cell layout
iv1v7x1
 
Effort
FO4 Log.
a /\ 1.04 1.07
¯_
iv1v7x1 schematic iv1v7x1 standard cell layout
iv1v8x1
 
Effort
FO4 Log.
a /\ 1.03 1.02
¯_
iv1v8x1 schematic iv1v8x1 standard cell layout
iv1v0x2
 
Effort
FO4 Log.
a /\ 1.00 1.01
¯_
iv1v0x2 schematic iv1v0x2 standard cell layout
iv1v1x2
 
Effort
FO4 Log.
a /\ 0.99 1.01
¯_
iv1v1x2 schematic iv1v1x2 standard cell layout
iv1v2x2
 
Effort
FO4 Log.
a /\ 1.00 1.00
¯_
iv1v2x2 schematic iv1v2x2 standard cell layout
iv1v4x2
 
Effort
FO4 Log.
a /\ 1.10 1.19
¯_
iv1v4x2 schematic iv1v4x2 standard cell layout
iv1v5x2
 
Effort
FO4 Log.
a /\ 1.04 1.06
¯_
iv1v5x2 schematic iv1v5x2 standard cell layout
iv1v6x2
 
Effort
FO4 Log.
a /\ 1.02 1.04
¯_
iv1v6x2 schematic iv1v6x2 standard cell layout
iv1v0x3
 
Effort
FO4 Log.
a /\ 0.97 1.00
¯_
iv1v0x3 schematic iv1v0x3 standard cell layout
iv1v3x3
 
Effort
FO4 Log.
a /\ 0.98 1.08
¯_
iv1v3x3 schematic iv1v3x3 standard cell layout
iv1v4x3
 
Effort
FO4 Log.
a /\ 1.08 1.15
¯_
iv1v4x3 schematic iv1v4x3 standard cell layout
iv1v5x3
 
Effort
FO4 Log.
a /\ 1.00 1.02
¯_
iv1v5x3 schematic iv1v5x3 standard cell layout
iv1v0x4
 
Effort
FO4 Log.
a /\ 0.96 0.99
¯_
iv1v0x4 schematic iv1v0x4 standard cell layout
iv1v1x4
 
Effort
FO4 Log.
a /\ 0.95 0.99
¯_
iv1v1x4 schematic iv1v1x4 standard cell layout
iv1v4x4
 
Effort
FO4 Log.
a /\ 1.09 1.17
¯_
iv1v4x4 schematic iv1v4x4 standard cell layout
iv1v5x4
 
Effort
FO4 Log.
a /\ 0.99 1.02
¯_
iv1v5x4 schematic iv1v5x4 standard cell layout
iv1v0x6
 
Effort
FO4 Log.
a /\ 0.96 0.98
¯_
iv1v0x6 schematic iv1v0x6 standard cell layout
iv1v3x6
 
Effort
FO4 Log.
a /\ 0.98 1.08
¯_
iv1v3x6 schematic iv1v3x6 standard cell layout
iv1v4x6
 
Effort
FO4 Log.
a /\ 1.07 1.16
¯_
iv1v4x6 schematic iv1v4x6 standard cell layout
iv1v5x6
 
Effort
FO4 Log.
a /\ 0.99 1.02
¯_
iv1v5x6 schematic iv1v5x6 standard cell layout
iv1v0x8
 
Effort
FO4 Log.
a /\ 0.96 0.99
¯_
iv1v0x8 schematic iv1v0x8 standard cell layout
iv1v1x8
 
Effort
FO4 Log.
a /\ 0.95 0.99
¯_
iv1v1x8 schematic iv1v1x8 standard cell layout
iv1v4x8
 
Effort
FO4 Log.
a /\ 1.08 1.16
¯_
iv1v4x8 schematic iv1v4x8 standard cell layout
iv1v5x8
 
Effort
FO4 Log.
a /\ 0.98 1.01
¯_
iv1v5x8 schematic iv1v5x8 standard cell layout
iv1v0x12
 
Effort
FO4 Log.
a /\ 0.96 0.98
¯_
iv1v0x12 schematic iv1v0x12 standard cell layout
iv1v4x12
 
Effort
FO4 Log.
a /\ 1.07 1.16
¯_
iv1v4x12 schematic iv1v4x12 standard cell layout
iv1v5x12
 
Effort
FO4 Log.
a /\ 0.98 1.01
¯_
iv1v5x12 schematic iv1v5x12 standard cell layout