dly1 standard cell family

non-inverting delay cells
dly1 symbol
The dly1 cell uses four chained inverters. The layout style maximises internal node parasitic capacitances, which contributes about 12ps of the dly1v0x05 fixed delay.
z:a cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
dly1v0x05 2.7  64 3.52  0.69  22.4  1.9f 145  4.95 154  3.83
dly1v0x05
 
Effort
FO4 Log.
a /\
¯_ 2.62
dly1v0x05 schematic dly1v0x05 standard cell layout