cgi2c standard cell family

carry generator inverting with 1 inverted input
cgi2c symbol
The output is the inverted carry of carry inputs a and b and the carry of input c. The stage efforts for pin c is 1.6, 1.9 and 2.4 for the x05, x1 and x2 drive strengths respectively. The cells here use a P/N ratio of about 2.
z:((a*b)+(a*c')+(b*c'))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgi2cv0x05 3.0  72 3.96  0.88  17.0  3.7f  72  7.35  86  5.32
cgi2cv0x1 3.0  72 3.96 1.37  25.6  5.0f  75  4.36  84  3.11
cgi2cv0x2 5.3 128 7.04 2.61  50.1  8.0f  75  2.11  83  1.34
cgi2cv0x3 8.3 200 11.00 3.97  74.4 11.6f  76  1.40  84  0.90
cgi2cv0x05
 
Effort
FO4 Log.
a /\ 2.78 3.63
¯_
b /\ 2.77 3.67
¯_
c /\
¯_ 2.47
cgi2cv0x05 schematic cgi2cv0x05 standard cell layout
cgi2cv0x1
 
Effort
FO4 Log.
a /\ 2.65 3.50
¯_
b /\ 2.66 3.59
¯_
c /\
¯_ 2.21
cgi2cv0x1 schematic cgi2cv0x1 standard cell layout
cgi2cv0x2
 
Effort
FO4 Log.
a /\ 2.73 3.69
¯_
b /\ 2.53 3.38
¯_
c /\
¯_ 1.92
cgi2cv0x2 schematic cgi2cv0x2 standard cell layout
cgi2cv0x3
 
Effort
FO4 Log.
a /\ 2.62 3.47
¯_
b /\ 2.54 3.41
¯_
c /\
¯_ 1.91
cgi2cv0x3 schematic cgi2cv0x3 standard cell layout