cgi2 standard cell family

carry generator inverting
cgi2 symbol
The output is the inverted carry of inputs a and b and carry input c, with the delay from pin c being favoured. The cells here use a P/N ratio of about 2.
These cells provide a carry propagation with low logical effort for pin c.
z:((a*b)+(a*c)+(b*c))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgi2v0x05 2.3  56 3.08  0.53   7.7  2.6f  57  7.33  53  5.31
cgi2v0x1 2.7  64 3.52  0.90  12.0  4.2f  54  4.34  50  3.10
cgi2v0x2 4.7 112 6.16 1.87  25.7  8.8f  56  2.10  47  1.33
cgi2v0x3 7.0 168 9.24 2.86  38.8 12.8f  56  1.40  48  0.90
cgi2v0x05
 
Effort
FO4 Log.
a /\ 2.77 3.63
¯_
b /\ 2.69 3.57
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c /\ 1.73 1.91
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cgi2v0x05 schematic cgi2v0x05 standard cell layout
cgi2v0x1
 
Effort
FO4 Log.
a /\ 2.65 3.50
¯_
b /\ 2.62 3.51
¯_
c /\ 1.64 1.82
¯_
cgi2v0x1 schematic cgi2v0x1 standard cell layout
cgi2v0x2
 
Effort
FO4 Log.
a /\ 2.72 3.68
¯_
b /\ 2.52 3.37
¯_
c /\ 1.60 1.75
¯_
cgi2v0x2 schematic cgi2v0x2 standard cell layout
cgi2v0x3
 
Effort
FO4 Log.
a /\ 2.61 3.46
¯_
b /\ 2.53 3.40
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c /\ 1.59 1.71
¯_
cgi2v0x3 schematic cgi2v0x3 standard cell layout