an4 standard cell family

4-I/P AND gate
an4 symbol
4 I/P AND gate designed with large (v0 version) and small (v4 version) input stages. The stage effort is 1.6 for the an4v0x05, is 1.9 for the an4v0x1, 2.2 for the an4v0x2, 2.6 for the an4v0x4 and 4.0 for the an4v4x1. The cells use a P/N ratio of about 2.5 for the NAND gates. The v0 cells are optimised for speed with typical wireload values, while the v4 cells are optimised for a zero wireload capacitance.
z:(a*b*c*d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an4v0x05 2.7  64 3.52  0.81  13.7  2.8f  91  5.04 101  3.90
an4v0x1 2.7  64 3.52 1.10  18.2  3.5f  89  3.34 100  2.58
an4v4x1 2.7  64 3.52  0.68  14.8  1.9f 112  3.39 132  2.66
an4v0x2 2.7  64 3.52 1.50  24.6  4.6f  90  2.16  99  1.67
an4v0x4 4.0  96 5.28 2.54  40.2  6.8f  88  1.09 101  0.84
an4v0x05
 
Effort
FO4 Log.
a /\
¯_ 2.45
b /\
¯_ 2.37
c /\
¯_ 2.24
d /\
¯_ 2.09
an4v0x05 schematic an4v0x05 standard cell layout
an4v0x1
 
Effort
FO4 Log.
a /\
¯_ 2.34
b /\
¯_ 2.23
c /\
¯_ 2.11
d /\
¯_ 1.96
an4v0x1 schematic an4v0x1 standard cell layout
an4v4x1
 
Effort
FO4 Log.
a /\
¯_ 2.51
b /\
¯_ 2.38
c /\
¯_ 2.24
d /\
¯_ 2.07
an4v4x1 schematic an4v4x1 standard cell layout
an4v0x2
 
Effort
FO4 Log.
a /\
¯_ 2.17
b /\
¯_ 2.09
c /\
¯_ 2.00
d /\
¯_ 1.86
an4v0x2 schematic an4v0x2 standard cell layout
an4v0x4
 
Effort
FO4 Log.
a /\
¯_ 2.11
b /\
¯_ 2.02
c /\
¯_ 1.89
d /\
¯_ 1.73
an4v0x4 schematic an4v0x4 standard cell layout