xnr2 standard cell family

2-I/P exclusive NOR gate
xnr2 symbol
2 XNOR gates designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnr2_x05 2.3  70 3.85  0.67  18.0  3.7f  82  4.84  78  3.68
xnr2_x1 2.3  70 3.85 1.22  31.6  6.2f  80  2.61  77  2.06
xnr2_x05
 
Effort
FO4 Log.
a /\ 1.68 1.46
¯_ 2.42
b /\ 2.04 2.58
¯_ 2.34
xnr2_x05 schematic xnr2_x05 standard cell layout
xnr2_x1
 
Effort
FO4 Log.
a /\ 1.62 1.37
¯_ 2.32
b /\ 1.95 2.48
¯_ 2.21
xnr2_x1 schematic xnr2_x1 standard cell layout