oai22 standard cell family

2×2-OR into 2-NAND gate
oai22 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The Ramp Fall time reported below is an average of when one or the other or both of the N-transistors connected to a1 and a2 are on. The Synopsys Liberty format .lib file has the precise timing for each case.
z:((a1+a2)*(b1+b2))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai22_x05 2.0  60 3.30  0.67   8.6  3.2f  55  5.83  48  3.81
oai22_x1 2.0  60 3.30 1.29  15.2  5.8f  52  2.99  47  2.02
oai22_x2 3.3 100 5.50 2.47  28.5 10.6f  52  1.58  46  1.04
oai22_x05
 
Effort
FO4 Log.
a1 /\ 2.01 1.90
¯_
a2 /\ 1.83 1.82
¯_
b1 /\ 1.83 1.93
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b2 /\ 1.64 1.82
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oai22_x05 schematic oai22_x05 standard cell layout
oai22_x1
 
Effort
FO4 Log.
a1 /\ 1.89 1.78
¯_
a2 /\ 1.72 1.70
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b1 /\ 1.74 1.81
¯_
b2 /\ 1.54 1.69
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oai22_x1 schematic oai22_x1 standard cell layout
oai22_x2
 
Effort
FO4 Log.
a1 /\ 1.86 1.77
¯_
a2 /\ 1.66 1.62
¯_
b1 /\ 1.70 1.77
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b2 /\ 1.50 1.61
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oai22_x2 schematic oai22_x2 standard cell layout