nr2 standard cell family

2-I/P NOR gate
nr2 symbol
The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr2_x05 1.3  40 2.20  0.32   5.6  3.1f  45  5.28  43  3.81
nr2_x1 1.3  40 2.20  0.70   9.2  5.2f  43  2.98  41  2.08
nr2_x2 2.0  60 3.30 1.39  16.0  9.8f  41  1.49  40  1.09
nr2_x05
 
Effort
FO4 Log.
a /\ 1.60 1.71
¯_
b /\ 1.43 1.63
¯_
nr2_x05 schematic nr2_x05 standard cell layout
nr2_x1
 
Effort
FO4 Log.
a /\ 1.52 1.61
¯_
b /\ 1.35 1.52
¯_
nr2_x1 schematic nr2_x1 standard cell layout
nr2_x2
 
Effort
FO4 Log.
a /\ 1.50 1.60
¯_
b /\ 1.30 1.48
¯_
nr2_x2 schematic nr2_x2 standard cell layout