nd3 standard cell family

 3-I/P NAND gate
nd3 symbol
The P:N ratio is set to 2.33. The fastest speed occurs when the shape factor r=√(KP÷KN×µ). For a 3-NAND gate, KP=1; KN=7/3, and for µ=9/4, r=√(27/28). We chooose to set r=1 instead, so the P:N ratio is close to the maximum speed, as well as giving balanced rise and fall drive strengths, with the P and N transistors having the same size.
z:(a*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3_x05 1.7  50 2.75  0.55   6.8  2.8f  52  4.94  41  4.24
nd3_x1 1.7  50 2.75  0.92  10.7  4.3f  50  2.96  40  2.54
nd3_x2 1.7  50 2.75 1.52  16.6  6.9f  49  1.80  39  1.54
nd3_x4 3.0  90 4.95 3.05  51.5 14.6f  62  0.90  41  0.77
nd3_x05
 
Effort
FO4 Log.
a /\ 1.56 1.52
¯_
b /\ 1.52 1.57
¯_
c /\ 1.40 1.48
¯_
nd3_x05 schematic nd3_x05 standard cell layout
nd3_x1
 
Effort
FO4 Log.
a /\ 1.50 1.45
¯_
b /\ 1.44 1.45
¯_
c /\ 1.33 1.39
¯_
nd3_x1 schematic nd3_x1 standard cell layout
nd3_x2
 
Effort
FO4 Log.
a /\ 1.45 1.40
¯_
b /\ 1.39 1.39
¯_
c /\ 1.28 1.33
¯_
nd3_x2 schematic nd3_x2 standard cell layout
nd3_x4
 
Effort
FO4 Log.
a /\ 1.24 1.29
¯_
b /\ 1.37 1.39
¯_
c /\ 1.44 1.41
¯_
nd3_x4 schematic nd3_x4 standard cell layout
Web data book for the vxlib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008