nd2a standard cell family

2-I/P NAND gate with inverted input
nd2a symbol
Single stage 2-I/P NAND gates with one inverted input. 2 drive strengths with a P:N ratio of 2.
z:(a+b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2a_x1 1.7  50 2.75 1.00   7.8  4.1f  44  2.96  35  2.16
nd2a_x2 1.7  50 2.75 1.92  14.2  7.5f  43  1.52  34  1.11
nd2a_x1
 
Effort
FO4 Log.
a /\
¯_ 1.66
b /\ 1.17 1.22
¯_
nd2a_x1 schematic nd2a_x1 standard cell layout
nd2a_x2
 
Effort
FO4 Log.
a /\
¯_ 1.54
b /\ 1.12 1.16
¯_
nd2a_x2 schematic nd2a_x2 standard cell layout