mxi2 standard cell family

Inverting 2-way multiplexers
mxi2 symbol
This style of 2-way mux has the smallest dimensions, although not the fastest speed. For fastest speed, the output should be driven through an inverter followed by a transfer gate. However, inserting the metal wire to join the P and N transistors of the inverters makes the cell wider (connecting n2 to n4 and n1 to n3 in the schematics below, and making sure that the transistors closest to the supply are connected to s or sn). The cells here use a P:N ratio of 2.
z:((a0*s')+(a1*s))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
mxi2_x05 2.3  70 3.85  0.98   9.1  3.3f  56  5.85  52  4.09
mxi2_x1 2.3  70 3.85 1.69  16.0  5.9f  53  3.08  50  2.18
mxi2_x05
 
Effort
FO4 Log.
a0 /\ 1.72 1.91
¯_
a1 /\ 1.84 2.00
¯_
s /\ 2.86 4.07
¯_ 3.19
mxi2_x05 schematic mxi2_x05 standard cell layout
mxi2_x1
 
Effort
FO4 Log.
a0 /\ 1.62 1.79
¯_
a1 /\ 1.73 1.85
¯_
s /\ 2.43 3.26
¯_ 2.83
mxi2_x1 schematic mxi2_x1 standard cell layout