iv1 standard cell family

inverter
iv1 symbol
A set of inverters with P/N ratio of 2 (iv1_x), 1.5 (iv1_w) and 2.25 (iv1_y). The P/N ratio of 2 offers good output skew, while 1.5 is close to the fastest speed and 2.25 is close to balanced output skews. The iv1_y2 is considered as the reference inverter for logical effort calculations.
z:a' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
iv1_x05 1.0  30 1.65  0.21   3.6  2.1f  40  4.92  36  3.80
iv1_x1 1.0  30 1.65  0.35   5.4  3.2f  39  2.95  35  2.27
iv1_w2 1.0  30 1.65  0.75  10.5  6.8f  39  1.52  31  0.88
iv1_x2 1.0  30 1.65  0.66   9.5  5.9f  38  1.56  34  1.20
iv1_y2 1.0  30 1.65  0.60   8.8  5.4f  38  1.64  36  1.42
iv1_x3 1.3  40 2.20  0.97  11.9  8.7f  37  1.06  33  0.81
iv1_x4 1.3  40 2.20 1.32  15.9 11.7f  36  0.78  33  0.60
iv1_x8 2.0  60 3.30 2.51  30.9 22.2f  37  0.41  33  0.32
iv1_x05
 
Effort
FO4 Log.
a /\ 1.07 1.06
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iv1_x05 schematic iv1_x05 standard cell layout
iv1_x1
 
Effort
FO4 Log.
a /\ 1.01 0.98
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iv1_x1 schematic iv1_x1 standard cell layout
iv1_w2
 
Effort
FO4 Log.
a /\ 0.97 0.95
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iv1_w2 schematic iv1_w2 standard cell layout
iv1_x2
 
Effort
FO4 Log.
a /\ 0.98 0.95
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iv1_x2 schematic iv1_x2 standard cell layout
iv1_y2
 
Effort
FO4 Log.
a /\ 1.00 0.96
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iv1_y2 schematic iv1_y2 standard cell layout
iv1_x3
 
Effort
FO4 Log.
a /\ 0.96 0.94
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iv1_x3 schematic iv1_x3 standard cell layout
iv1_x4
 
Effort
FO4 Log.
a /\ 0.96 0.94
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iv1_x4 schematic iv1_x4 standard cell layout
iv1_x8
 
Effort
FO4 Log.
a /\ 0.96 0.94
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iv1_x8 schematic iv1_x8 standard cell layout