oai211 standard cell family

 2-OR into 3-NAND gate
oai211 symbol
2 cells with different drive strengths, each with a P/N ratio of about 2. The width of the P-transistors connected to pins b and c are designed to have a similar conductivity to the two series P-transistors, so that there is a consistent output drive capability.
z:((a1+a2)*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai211v0x05 2.0  48 2.64  0.51  11.2  2.9f  84  7.33  56  5.14
oai211v0x1 2.3  56 3.08  0.85  17.6  4.6f  80  4.34  52  3.03
oai211v0x05
 
Effort
FO4 Log.
a1 /\ 2.24 2.25
¯_
a2 /\ 2.04 2.11
¯_
b /\ 1.61 1.61
¯_
c /\ 1.50 1.54
¯_
oai211v0x05 schematic oai211v0x05 standard cell layout
oai211v0x1
 
Effort
FO4 Log.
a1 /\ 2.13 2.15
¯_
a2 /\ 1.93 1.98
¯_
b /\ 1.49 1.44
¯_
c /\ 1.43 1.46
¯_
oai211v0x1 schematic oai211v0x1 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008