nr3a standard cell family

 3-I/P NOR gate with inverted input
nr3a symbol
Minimum size 3-I/P NOR gate with an inverted input. The output P/N ratio is about 1.7, and the gain from input a is about 1.6.
z:(a'+b+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr3av0x05 2.3  56 3.08  0.81   7.3  3.6f  51  6.23  48  3.88
nr3av0x05
 
Effort
FO4 Log.
a /\
¯_ 2.46
b /\ 2.03 2.20
¯_
c /\ 1.77 2.14
¯_
nr3av0x05 schematic nr3av0x05 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008