lant1 standard cell family

 Rising clock edge D flip-flop
lant1 symbol
Latch with x05 and x1 drive strengths non-inverted output, transparent when enable pin e is high. Clocked inverters are used on the input and feedback nodes. The power numbers are given at the clock frequency both when the output is stable and when it changes. The setup and hold times are the maximum for pin d transition times up to 1500ps and for clock pin e up to 670ps. The fanout 4 values are those when the z output drives the e and d inputs.
z:latch(e,d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin e-z.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap   Prop Ramp Setup Hold
lant1v0x05 3.3  80 4.40  0.76 clock only   4.3 e  4.0f Rise  98  5.07 380  -27
state change  25.7 d  2.4f Fall 169  4.19 365 -0
lant1v0x1 3.3  80 4.40  0.87 clock only   4.3 e  4.0f Rise 105  3.41 383  -33
state change  28.1 d  2.4f Fall 178  2.86 351 -10
lant1v0x05
 
FO4 Effort
e 2.45
d 2.54
lant1v0x05 schematic lant1v0x05 standard cell layout
lant1v0x1
 
FO4 Effort
e 2.39
d 2.47
lant1v0x1 schematic lant1v0x1 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2007 Graham Petley.  11 JAN 2008