cgi2b standard cell family

 carry generator inverting with 1 inverted input
cgi2b symbol
The output is the inverted carry of carry inputs a and c and the carry of input b. The stage efforts for pin b is 1.6, 1.9 and 2.4 for the x05, x1 and x2 drive strengths respectively. The cells here use a P/N ratio of about 2.
z:((a*b')+(a*c)+(b'*c))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgi2bv0x05 3.0  72 3.96  0.88   7.7  2.6f  57  7.34  53  5.33
cgi2bv0x1 3.0  72 3.96 1.37  11.9  4.2f  54  4.34  49  3.11
cgi2bv0x2 5.3 128 7.04 2.61  25.8  8.8f  56  2.10  47  1.34
cgi2bv0x3 8.3 200 11.00 3.97  38.8 12.8f  55  1.40  47  0.90
cgi2bv0x05
 
Effort
FO4 Log.
a /\ 2.78 3.64
¯_
b /\
¯_ 2.88
c /\ 1.73 1.91
¯_
cgi2bv0x05 schematic cgi2bv0x05 standard cell layout
cgi2bv0x1
 
Effort
FO4 Log.
a /\ 2.65 3.51
¯_
b /\
¯_ 2.55
c /\ 1.64 1.82
¯_
cgi2bv0x1 schematic cgi2bv0x1 standard cell layout
cgi2bv0x2
 
Effort
FO4 Log.
a /\ 2.73 3.69
¯_
b /\
¯_ 2.27
c /\ 1.60 1.75
¯_
cgi2bv0x2 schematic cgi2bv0x2 standard cell layout
cgi2bv0x3
 
Effort
FO4 Log.
a /\ 2.62 3.47
¯_
b /\
¯_ 2.26
c /\ 1.58 1.71
¯_
cgi2bv0x3 schematic cgi2bv0x3 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008