aoi22 standard cell family

2x 2-AND into 2-NOR gate
aoi22 symbol
6 cells with different drive strengths, each with a P/N ratio of about 2. The Ramp Rise time reported below is an average of when one or the other or both of the P-transistors connected to pins a1 and a2 are on. The Synopsys Liberty format .lib file has the precise timing for each case. The aoi22v5x05 is a layout variation of the aoi22v0x05.
z:((a1*a2)+(b1*b2))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi22v0x05 2.3  56 3.08  0.53   6.3  2.7f  53  6.65  47  5.29
aoi22v5x05 2.3  56 3.08  0.53   6.3  2.8f  54  6.65  48  5.29
aoi22v0x1 2.3  56 3.08  0.90   9.7  4.3f  50  3.94  45  3.10
aoi22v0x2 4.0  96 5.28 1.87  20.1  8.5f  50  1.90  44  1.49
aoi22v0x3 6.0 144 7.92 2.82  29.3 13.0f  50  1.27  44  0.98
aoi22v0x4 7.7 184 10.12 3.74  39.7 17.1f  50  0.95  44  0.74
aoi22v0x05
 
Effort
FO4 Log.
a1 /\ 2.05 1.95
¯_
a2 /\ 2.02 1.95
¯_
b1 /\ 1.74 2.00
¯_
b2 /\ 1.64 1.88
¯_
aoi22v0x05 schematic aoi22v0x05 standard cell layout
aoi22v5x05
 
Effort
FO4 Log.
a1 /\ 2.09 2.10
¯_
a2 /\ 1.94 1.88
¯_
b1 /\ 1.71 1.93
¯_
b2 /\ 1.67 1.92
¯_
aoi22v5x05 schematic aoi22v5x05 standard cell layout
aoi22v0x1
 
Effort
FO4 Log.
a1 /\ 1.94 1.82
¯_
a2 /\ 1.91 1.85
¯_
b1 /\ 1.61 1.81
¯_
b2 /\ 1.55 1.78
¯_
aoi22v0x1 schematic aoi22v0x1 standard cell layout
aoi22v0x2
 
Effort
FO4 Log.
a1 /\ 1.92 1.83
¯_
a2 /\ 1.83 1.73
¯_
b1 /\ 1.60 1.80
¯_
b2 /\ 1.50 1.67
¯_
aoi22v0x2 schematic aoi22v0x2 standard cell layout
aoi22v0x3
 
Effort
FO4 Log.
a1 /\ 1.88 1.80
¯_
a2 /\ 1.81 1.72
¯_
b1 /\ 1.55 1.72
¯_
b2 /\ 1.50 1.69
¯_
aoi22v0x3 schematic aoi22v0x3 standard cell layout
aoi22v0x4
 
Effort
FO4 Log.
a1 /\ 1.90 1.81
¯_
a2 /\ 1.82 1.73
¯_
b1 /\ 1.55 1.72
¯_
b2 /\ 1.51 1.68
¯_
aoi22v0x4 schematic aoi22v0x4 standard cell layout