na3 standard cell family

3-I/P NAND gate
na3 symbol
The na3_x1 is a single stage 3-NAND with P/N ratio of about 2.3, which makes the P and N transistors the same size. The na3_x4 is a 3 stage 3-NAND with stage efforts of about 1.1 and 3.9.
nq:(i0*i1*i2)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
na3_x1 1.7  50 2.75  0.92  11.2  4.5f  52  2.97  44  2.83
na3_x4 2.7  80 4.40 2.66  61.0  4.9f 156  0.76 157  0.61
na3_x1
 
Effort
FO4 Log.
i0 /\ 1.53 1.49
¯_
i1 /\ 1.50 1.54
¯_
i2 /\ 1.43 1.51
¯_
na3_x1 schematic na3_x1 standard cell layout
na3_x4
 
Effort
FO4 Log.
i0 /\ 2.33 0.38
¯_
i1 /\ 2.52 0.39
¯_
i2 /\ 2.44 0.39
¯_
na3_x4 schematic na3_x4 standard cell layout