inv standard cell family

inverter
inv symbol
4 inverters with P/N ratios of 2 (inv_x1, inv_x8), 1.5 (inv_x2) and 1.7 (inv_x4). The inv_x2 is considered as the reference inverter for logical effort calculations.
nq:i' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
inv_x1 1.0  30 1.65  0.35   5.7  3.5f  40  2.96  36  2.27
inv_x2 1.0  30 1.65  0.58   8.8  5.6f  40  1.97  32  1.14
inv_x4 1.3  40 2.20 1.36  14.7 11.0f  37  0.90  32  0.64
inv_x8 2.3  70 3.85 2.77  31.9 23.5f  36  0.38  34  0.32
inv_x1
 
Effort
FO4 Log.
i /\ 1.06 1.06
¯_
inv_x1 schematic inv_x1 standard cell layout
inv_x2
 
Effort
FO4 Log.
i /\ 1.01 1.01
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inv_x2 schematic inv_x2 standard cell layout
inv_x4
 
Effort
FO4 Log.
i /\ 0.98 0.98
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inv_x4 schematic inv_x4 standard cell layout
inv_x8
 
Effort
FO4 Log.
i /\ 0.97 0.95
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inv_x8 schematic inv_x8 standard cell layout