ao2o22 standard cell family

2×2-OR into 2-AND gate
ao2o22 symbol
2-2 I/P OR-AND gate with a stage effort of about 3.5 for the ao2o22_x2, and about 7 for the ao2o22_x4.
q:((i2+i3)*(i0+i1)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
ao2o22_x2 3.0  90 4.95 1.39  29.4  3.7f 103  1.52 145  1.24
ao2o22_x4 3.3 100 5.50 2.08  46.2  3.5f 131  0.77 190  0.64
ao2o22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.21
i1 /\
¯_ 2.07
i2 /\
¯_ 2.33
i3 /\
¯_ 2.49
ao2o22_x2 schematic ao2o22_x2 standard cell layout
ao2o22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.59
i1 /\
¯_ 2.44
i2 /\
¯_ 2.70
i3 /\
¯_ 2.87
ao2o22_x4 schematic ao2o22_x4 standard cell layout